Method and apparatus of burst read and pipelined dynamic random access memory having multiple pipelined stages with DRAM controller and buffers integrated on a single chip

摘要

A single-chip integrated DRAM memory system having a high density and large bandwidth. The single-chip DRAM system includes a DRAM array 10 having a plurality of pipelined stages 12, a control logic 11 for controlling said DRAM array 10 and a buffer 13 integrated onto chip for storing data being fetched from said DRAM array. The DRAM array, control logic, and the buffer are all integrated onto one and the same substrate 1. The control logic 11 generates a control signal for controlling operations taking place in the plurality of pipelined stages and the final stage of said pipeline 12 inputs/outputs data from said buffer means 13 in a burst mode.