Memory array architecture and method for dynamic cell plate sensing

摘要

A memory array architecture is described which uses active digit lines at array edges. To maximize array area using active digit lines, a memory array architecture is employed where interior rows of memory cells intersect X columns of memory cells. Rows located along the edge of the array, however, intersect less than X columns of memory cells. Two rows of memory cells located along the edge of the array must be accessed together to form a complete row of X columns.