Data buffer for programmable memory with several conditions

摘要

The data buffer has a read amplifier and a data register array (10). Several upper (20-1) and lower read/write circuits (20-2) are connected between the data register array and the input/output buffers and read amplifiers, respectively. An upper (30-1) and a lower circuit (30-2) connect the data register array with the upper and/or with the lower read/write circuits. The data buffer has a read amplifier formed in several columns for the temporary storing of data, and a data register array (10) configured according to an amount of input/output buffer pins, whereby each array comprises rows according to the number of cells which are to be processed through each read amplifier. Several upper read/write circuits (20-1) are connected between the data register array and the input/output buffers. Several lower read/write circuits (20-2) are connected between the data register array and the read amplifiers. An upper (30-1) and a lower circuit (30-2) connect the data register array with the upper and/or with the lower read/write circuits. A decoder (40) with several outputs selects several word conductors of the data register array.