| 摘要 |
PROBLEM TO BE SOLVED: To ensure a high working precision in the fabrication of a semiconductor device by constituting a working precision verifying mark by a mark of the same form as a layout data present in a logic area. SOLUTION: A working precision verifying mark is formed of a first mark of the same form as one of layout data present in a logic area, or a second mark having at least two or more closely arranged first marks. For example, two working precision verifying layout patterns 100, 101 for semiconductor device are provided. The dimensional measurement data of hole data for a single contact or the like can be performed by the layout pattern 100, and the dimensional measurement of hole data for close contacts or the like can be performed by the layout pattern 101. Thus, the error between the dimension of an actual layout pattern and the dimension of the working precision verifying layout pattern can be minimized to ensure a highly precise dimension. |
