Hardware-managed programmable congruence class caching mechanism

摘要

A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. A logic unit is connected to the cache for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes are then defined using a mapping function which operates on the encoded addresses, such that the logic unit may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The logic unit can modify the original addresses by setting a plurality of programmable fields. The logic unit also can collect information on cache misses, and modify the original addresses in response to the cache miss information. In this manner, a procedure running on the processor and allocating memory blocks to the cache such that the original addresses, if applied to the mapping function, would result in striding of the cache, runs more efficiently by using the encoded addresses to result in less striding of the cache.