| 摘要 |
<p>A method and apparatus is described for recovering data sample clock rates from received isochronous streams of data packets including associated time stamp values, such as in an IEEE 1394 bus-interconnected system. The difference between consecutive time stamp values is determined by successively latching the time stamp values and applying them to a subtracter circuit to produce a difference value. This difference value is then successively decremented by a down counter, with the down counter then producing a signal pulse and loading a next difference value upon completion of the count. The pulsed signal is applied to a phase-locked loop to provide a frequency multiple, and a clock signal is correspondingly produced that has a frequency proportional to the difference between the consecutive time stamp values. Data input buffer levels may be monitored and the clock signal frequency adjusted accordingly.</p> |
