Layout structure of multi-use coupling capacitors in reducing ground bounces and replacing faulty logic components

摘要

A first mask includes a well mask formed over a first portion of the wafer to define a first conductive type well in the wafer. A first polysilicon mask is formed over the well mask including a plurality of first structures and a plurality of second structures to cover a first polysilicon layer, thereby defining polysilicon gates. A first implanting mask is formed over the first polysilicon mask for forming second conductive type region. A second implanting mask is formed over the first polysilicon mask for forming first conductive type region. A second polysilicon mask is formed between gates of a second conductive type MOS and gates of a first conductive type MOS. A contact hole mask is formed over the second polysilicon mask for forming contact holes. A metal mask is formed over the contact hole mask for forming connection.