发明名称 |
Programmable logic device with multi-port memory |
摘要 |
An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.
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申请公布号 |
US6011744(A) |
申请公布日期 |
2000.01.04 |
申请号 |
US19970895516 |
申请日期 |
1997.07.16 |
申请人 |
ALTERA CORPORATION;QUICKTURN DESIGN SYSTEMS, INC. |
发明人 |
SAMPLE, STEPHEN P.;BUTTS, MICHAEL R.;NORMAN, KEVIN A.;PATEL, RAKESH H.;CHEN, CHAO CHIANG |
分类号 |
G11C7/10;G11C7/22;G11C8/16;H03K19/177;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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