DESIGNING METHOD FOR FACILITATING CHECK FOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To facilitate the generation of a check sequence rather than a conventional case concerning a designing method for facilitating check for identifying a scanning FF. SOLUTION: An FF relation graph is prepared from an integrated circuit (SA1) and after FF composing of a self-loop are recognized from this FF relation graph (SA2), all the FF are scanned (SA3). According to a prescribed evaluation index expressing the degree of relation with difficulty in the check sequence generation, all the FF not composing of the self-loop are sorted (SA4). For example, an index expressing the degree of relation with a balance reconverging structure is used as the evaluation index. When it is assumed that the respective FF not composing of the self-loop are not scanned in this sort order, it is discriminated whether the integrated circuit is made into n-times arranged structure or not and it is determined whether or not the FF are to be scanned (SA5-SA8).