| 摘要 |
PROBLEM TO BE SOLVED: To effectively attain the adiabatic charging logic together with reduction of a wiring sectional area and accordingly to reduce both power consumption and scale of an adiabatic charging logic circuit. SOLUTION: The input voltage *A, *B, *C, A, B and C are inputted to the gate of each n-channel MOSFET 8 of a BDD(binary decision diagram) logic circuit at time t = 0. Then the output voltage of a power reuse type power supply 10 is slowly raised to adiabatically charge the BDD logic circuit. This charging performs a logical operation to acquire an output signal. Then the output voltage of the supply 10 is slowly dropped after the adiabatic charging. Meanwhile, the electric charge stored in the BDD logic circuit is returned again to the supply 10. The next input signal is inputted via the gate at time t = T that is set after the output potential of the BDD logic circuit is set at a low level. Thereafter, this operation is repeated in a cycle T to execute the adiabatic charging and an electric charge recycle.
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