| 摘要 |
A bandpass SIGMA DELTA DC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, or a two-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMA DELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMA DELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMA DELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion. |
