发明名称 SIGNAL PROCESSING CIRCUIT AND INFORMATION RECORDING DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce memory capacity in a memory area of recoded data by switching alternately a data area added with parity storing recorded data after addition of the parity and a transmission area reading out and transmitting the recorded data after addition of the parity and by starting the addition of the parity to the recorded data corresponding to reception of the recorded data of one row volume of an error correction code. SOLUTION: Recorded data are written in a storing area A in the third phase next to the second phase similarly with the first phase, and the recorded data are read out each time of writing the recorded data of one row volume of an error correction code, and a process adding a parity of the error correction code is executed. On the other hand, the recorded data added with the parity at the second phase are read out from a storing area B and are transmitted. Thus, when one of the two storing areas A or B executes reception of the recorded data and addition of the parity, the other executes read-out and transmission processes of recorded data after addition of the parity, and this execution is switched alternately with a phase unit.
申请公布号 JP2000331439(A) 申请公布日期 2000.11.30
申请号 JP19990135351 申请日期 1999.05.17
申请人 TOSHIBA AVE CO LTD;TOSHIBA CORP 发明人 KODAMA KUNIHIKO
分类号 G11B20/18;(IPC1-7):G11B20/18 主分类号 G11B20/18
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