| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of lowering an output node to a desired voltage without increasing a chip size and current consumption. SOLUTION: This semiconductor integrated circuit is provided with PMOS transistors Q1, Q2 and an NMOS transistor Q3. The source terminal of the PMOS transistor Q1 is connected to an output node OUT and the drain terminal of the transistor is connected to a grounding terminal. An external power source voltage Vcc is applied to the source terminal of the PMOS transistor Q2 and the drain terminal of the transistor is connected to the output node OUT. The source terminal of the NMOS transistor Q3 is connected to the output node OUT and the negative voltageϕL outputted from a negative voltage generating circuit is applied to the drain of the transistor. At the time of lowering the output node OUT till the negative voltageϕL, since the node OUT is short- circuited once, the electric charge stored in the parasitic capacity of the node OUT can be quickly drawn out to the grounding terminal.
|
