| 摘要 |
PROBLEM TO BE SOLVED: To downsize a CMOS transfer circuit and facilitate its layout. SOLUTION: In a layout of a CMOS transfer circuit (transfer gate type/ inverter type) for transferring prescribed potentials to word lines, p-channel MOS transistors are formed on n-type well regions 32, on which signal lines 56 (signal lines and control signal line pairs Mx, MxB connected to the word lines) extending in the row directions are laid on a first wiring layer and signal lines 56 (control signal lines BiJj and signal line VBBBi)) extending in the columnar directions are laid on a second wiring layer. N-channel MOS transistors are formed on p-type well regions 33, on which signal lines (control signal lines BiFj and signal lines VBBBi) extending in the columnar directions are laid on a first wiring layer and signal lines 57 (signal lines and control signal line pairs Mx, MxB connected to ward lines) extending in the row directions, are laid on a second wiring layer.
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