发明名称 DEVICE FOR EVALUATING LINEAR LAYOUT OF COMPONENTS
摘要 computer engineering; computer-aided design. SUBSTANCE: device has memory unit, circuit length computing units, maximum locating unit, loading assessment units, ones counting unit, adder, maximum discrimination unit, and AND gate. Device provides for computing criterion of layout area loading. EFFECT: enlarged functional capabilities. 10 dwg
申请公布号 RU2163028(C2) 申请公布日期 2001.02.10
申请号 RU19990107942 申请日期 1999.04.13
申请人 IVERSITET;IVERSITET 发明人 RYBAL'CHENKO M.V.;GLUSHAN' V.M.
分类号 G06F17/30;(IPC1-7):G06F17/30 主分类号 G06F17/30
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