发明名称 VIDEO SIGNAL PROCESSING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a video signal processing circuit whose circuit scale and power consumption can be reduced. SOLUTION: This video signal processing circuit is constituted of a CCD 21, a clamp and hold circuit 22, an A/D converter 23, a driving circuit 24, and a timing generating circuit 25. Thus, the video signal processing circuit is constituted by using not a correlative double sampling circuit using plural amplifiers, buffers, and switches or the like constituting a conventional video signal processing circuit but the clamp and hold circuit so that an equivalent video signal noise removing function can be realized in a smaller circuit scale than that of the conventional video signal processing circuit.
申请公布号 JP2001045325(A) 申请公布日期 2001.02.16
申请号 JP19990214205 申请日期 1999.07.28
申请人 NEC CORP 发明人 URAYAMA YOJI
分类号 H04N5/18;H04N5/335;H04N5/341;H04N5/357;H04N5/363;H04N5/372;H04N5/376;H04N5/378;(IPC1-7):H04N5/18 主分类号 H04N5/18
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