发明名称 METHOD FOR REDUCING ISO-EFFICIENCY CRITICAL DIMENSION FOR MASK BY POLYMER DEPOSITION AND ETCHING IN THE SAME POSITION
摘要 PROBLEM TO BE SOLVED: To effectively reduce the critical dimension of a semiconductor element by stepwise coating a polymer layer with openings and wires, increasing the ratio of height and width on one wire and one opening with the polymer layer and reducing the critical dimension of photoresist. SOLUTION: A polymer layer 26 is formed on photoresist 21 by a plasma reactor. The material of the polymer layer 26 is selected by carbon fluoride, hydrocarbon fluoride and carbide. A deposition process and an etching process are simultaneously advanced in the same environment in the plasma reactor. The polymer layer 26 is filled in one structure 25 with stepwise coating ability and it does not coat the base part of one structure 25. Thus, the ratio of height to width in one structure 25 can reduce the critical dimension of photoresist 21 from W6 to W7 by the polymer layer 26 coating photoresist 21 by the increase of the polymer layer 26.
申请公布号 JP2001053062(A) 申请公布日期 2001.02.23
申请号 JP19990225215 申请日期 1999.08.09
申请人 UNITED MICROELECTRONICS CORP 发明人 SAI MEIKAN;YO KENRIN
分类号 H01L21/302;C23C16/50;H01L21/027;H01L21/3065;H01L21/31;H01L21/311;(IPC1-7):H01L21/306 主分类号 H01L21/302
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