发明名称 Multi-input and binary reproducible, high bandwidth floating point adder in a collective network
摘要 To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to the collective logic device and receive outputs only once from the collective logic device.
申请公布号 US9495131(B2) 申请公布日期 2016.11.15
申请号 US201514641765 申请日期 2015.03.09
申请人 International Business Machines Corporation 发明人 Chen Dong;Eisley Noel A.;Heidelberger Philip;Steinmacher-Burow Burkhard
分类号 G06F7/38;G06F9/38;G06F9/30;G06F7/485 主分类号 G06F7/38
代理机构 Scully, Scott, Murphy & Presser, P.C. 代理人 Scully, Scott, Murphy & Presser, P.C. ;Morris, Esq. Daniel P.
主权项 1. A method for adding a plurality of first floating point (FP) numbers in a parallel computing system, the system comprising a plurality of computing nodes, a computing node including at least one processor and at least one memory device, and a collective logic device, the method comprising: receiving, at the front-end logic device, a plurality of the first floating point numbers in parallel from the computing nodes or network links; converting, by said front-end device, the first floating point numbers to a plurality of integer numbers, said front-end logic device further for comparing exponents of each of the first floating point numbers to determine a maximum exponent; adding, using an ALU comprising a plurality of levels with combining blocks, the integer numbers in parallel and generating a summation of all of the plurality of integer numbers in one pass; and converting, at a back-end logic device, the summation to a second floating point number by performing shifting according to the maximum exponent; and providing, by one or more arbiter devices, configuration bits to front-end logic device for configuring said front-end logic device with a number of FP shifters used for said converting said first FP numbers to said integer numbers, and for configuring said ALI to perform an addition of the integer numbers, at least one arbiter device performing a method including: arbitrating among first, second and third traffic types, and choosing an input request from one of the first, second and third traffic types, andresponsive to choosing an input request, sending the chosen input request to at least one reception FIFO for permission, andresponsive to receipt of a permission grant from the at least one of the reception FIFO, sending the permitted input request to a sub-arbitrator device and to at least one injection FIFO.
地址 Armonk NY US