TEST INTERFACE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME

摘要

PROBLEM TO BE SOLVED: To provide a test interface circuit for mixed memory in which the number of test data input/output terminals is reduced and a practicable test pattern is increased. SOLUTION: A test interface circuit TIC provided between a mixed memory MCR and a test data input/output terminal 9 is provided with a first-in/first-out circuit 10 storing successively test data, and latency of data read out from the mixed memory is adjusted.