| 摘要 |
PROBLEM TO BE SOLVED: To provide a circuit delay analyzing method, which is highly accurate and enables the short processing time as well. SOLUTION: The circuit delay analyzing method for analyzing circuit delay by applying a static timing analyzing method to plural circuit units connected between two selected nodes, has a first step for designating plural input patterns for monotonously changing the time of delay between the nodes corresponding to previously calculated delay characteristics for each circuit unit, a second step for successively verifying logic levels, which a signal transmitted between the nodes can actually have, corresponding to the plural input patterns specified in the first step, and a third step for calculating the time of delay realized between the nodes on the basis of the verification in the second step.
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