发明名称 |
POST-SILICON VALIDATION AND DEBUG USING SYMBOLIC QUICK ERROR DETECTION |
摘要 |
Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called "change detectors" which introduce only a small area overhead. Symbolic QED exhibits: 1) A systematic (and automated) approach to inserting "change detectors" during a design phase; 2) Quick Error Detection (QED) tests that detect bugs with short error detection latencies and high coverage; and 3) Formal techniques that enable bug localization and generation of minimal bug traces upon bug detection. |
申请公布号 |
WO2016200723(A1) |
申请公布日期 |
2016.12.15 |
申请号 |
WO2016US35987 |
申请日期 |
2016.06.06 |
申请人 |
THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY |
发明人 |
MITRA, Subhasish;BARRETT, Clark;LIN, David;SINGH, Eshan |
分类号 |
G06F11/273;G06F11/30;H01L21/66 |
主分类号 |
G06F11/273 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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