FAILURE-VERIFYING METHOD AND DEVICE

摘要

PROBLEM TO BE SOLVED: To improve reliability and efficiency of failure detection performed, when semiconductor circuits such as LSIs are subjected to at shipment tests delivery tests. SOLUTION: A signal collision occurrence section with signal values which becomes indeterminate is cut out from among failure-detected sections with a possibility of failure occurrence extracted from the connection information of a logical circuit included in a circuit to be tested. The cut-out signal collision occurrence section is subjected to circuit verification. The contents of operation are tabulated and stored in an operation state table 20. By making reference to a tabulated operation state table 20, the logical value of the signal collision section is determined to eliminate an indeterminate state with signal values indeterminate from the circuit to be tested, and pseudo logical operation and validity verifying operation are executed on the circuit to be tested.