发明名称 DATA PROCESSOR
摘要 PROBLEM TO BE SOLVED: To enable bus control corresponding to a bus width for every module regardless of a change in the address location of the module. SOLUTION: A first module (1) is provided with a data transfer control circuit (1A) and second modules (2, 3 and 4) are provided with bus width reporting circuits (2A, 3A and 4A). When bus width information required for data transfer is reported from the second module to the first module, on the basis of the reported bus width information, in the first module, bus control is performed for data transfer to be executed with the second module. Thus, bus control corresponding to the bus width for every module can be performed regardless of a change in the address location of the module.
申请公布号 JP2002073533(A) 申请公布日期 2002.03.12
申请号 JP20000255125 申请日期 2000.08.25
申请人 HITACHI LTD 发明人 NAKAYAMA HARUYUKI;MITSUISHI NAOMIKI
分类号 G06F13/36;(IPC1-7):G06F13/36 主分类号 G06F13/36
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