| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device and its I/O cell layout method whereby the measures for reducing its chip area and increasing the number of its pins are made possible without altering its inner core transistor region. SOLUTION: A semiconductor chip 110 of the semiconductor device has a core transistor region 112, an I/O-cell layout region 114, and a pad layout region 116. I/O cells 120 disposed in each side of the I/O-cell layout region 114 of the semiconductor chip 110 are so arranged that the number of their stages vertical to the arrangement direction of pads 122 arranged along each side of the outer edge portion of the semiconductor chip 110 is made two or more and their longitudinal arrangement directions (height directions) are made respectively parallel with the arrangement direction of the pads 122. |
