| 摘要 |
A clock signal generator for generating a clock signal with minimum phase jitter at a clock signal generator output (41), the clock signal generator (1) having: a DT oscillator (4) which is clocked with an input clock signal and generates a periodic digital DTO output signal, a phase displacement calculation unit (12) for calculating the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit MSB of the DTO output signal, and a phase displacement reduction unit for reducing the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit MSB of the DTO output signal as a function of the calculated phase displacement, the most significant bit MSB being output with reduced phase displacement as a clock signal to the clock signal generator output (41).
|
