| 摘要 |
A counter circuit, which is capable of operating at high speed and realizing a sequential binary count order, and a counting method thereof are provided. The counter circuit includes a first bit generation circuit, a second bit generation circuit, a third bit generation circuit, and a fourth bit generation circuit. The first bit generation circuit includes a D-flip-flop, inverts its output value every cycle of the clock signal, and generates a first bit output. The second bit generation circuit includes two D-flip-flops, inverts its output value every two cycles of the clock signal, and generates a second bit output. The third bit generation circuit includes four D-flip-flops, inverts its output value every four cycles of the clock signal, and generates a third bit output. The fourth bit generation circuit includes eight D-flip-flops, inverts its output value every eight cycles of the clock signal, and generates a fourth bit output. According to the counter circuit, bit outputs are generated with almost the same delay time within one cycle of a clock signal in a sequential binary count order. Thus, the operation of a system can be prevented from being delayed, and the performance of the system can be improved.
|
