Capacitively coupled DTMOS on SOI

摘要

A transistor structure is provided comprising a source region having a N+ source region and a N- lightly doped source region. The structure also comprises a drain region having a N+ drain region and a N- lightly doped drain region. A P++ heavily doped region is provided. The P++ region resides alongside at least a portion of at least one of the N- lightly doped source region and N- lightly doped drain region. A P+ body region resides below a gate of the device and between the source and drain regions. The P+⇄ heavily doped region provides a capacitive coupling between a body region and the gate of the device and form a capacitive voltage divider with the junction capacitance of the device.