发明名称 DELAY LOCK LOOP CIRCUIT, VARIABLE DELAY CIRCUIT, AND RECORDING SIGNAL COMPENSATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a delay lock loop circuit which can stably obtain a fine delay amount, independently of the variation of the temperature and the power source voltage or the variation of a delay amount due to the process conditions and so forth. SOLUTION: A count value BIC is counted up or counted down from a set initial value BIC-INT to a set maximum value BIC-MAX or to a set minimum value BIC-MIN, on the basis of an up-and-down control signal UD from a delay amount detection means, in which a noise component of the up-and-down control signal UD is cut, by respectively performing the count-up and the countdown of a count value SEL when the count value BIC becomes the maximum value or the minimum value. Accordingly, a delay lock detection part supplied with the count value SEL operates normally, independently of the variation of the delay amount due to a delay line, and a reference delay stage number for obtaining a delay of IT is stably outputted.
申请公布号 JP2002324369(A) 申请公布日期 2002.11.08
申请号 JP20010163818 申请日期 2001.05.31
申请人 SONY CORP 发明人 ENDO MAKI
分类号 G11B7/0045;G11B20/14;H03L7/081;H03L7/095;(IPC1-7):G11B20/14;G11B7/004 主分类号 G11B7/0045
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