| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device for which the timing control can be facilitated and a layout size is reduced by arranging a word line drivers at one side of a memory cell array. SOLUTION: In this semiconductor memory device, a first word line driver region WD1 at one side, and a second word line driver region WD2 at the other side are arranged sandwiching an address signal line region RA. On the opposite side of the address signal line region RA of the first word line driver region WD1, a memory cell array CA is arranged. Output signal lines of word line drivers in the second word line driver region WD2 are electrically connected to word lines WL on the memory cell array CA through third metal wirings M3 formed so as to cross the address signal line region RA.
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