Modulation circuit and operating method thereof

摘要

A modulation circuit includes a phase locked loop (PLL) circuit, a scalar circuit and a sigma-delta modulator. The PLL circuit is for generating an output oscillating signal in response to a reference signal, a first control signal and a second control signal. The scalar circuit is for generating the first control signal in response to modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form. The sigma-delta modulator is for generating the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit.

主权项

1. A modulation circuit, comprising:
a phase locked loop (PLL) circuit, for generating an output oscillating signal in response to a reference signal, a first control signal and a second control signal, the PLL circuit comprises: a phase frequency detector, for detecting a phase difference between the reference signal and a divided signal; a charge pump coupled to the phase frequency detector; a loop filter, coupled to the charge pump, for outputting a filtered signal in response to the phase difference; an oscillating module, for generating the output oscillating signal in response to the filtered signal and the first control signal, comprising: a digital controlled capacitor bank, wherein the first control signal controls the capacitance of the digital controlled capacitor bank to adjust a frequency of the output oscillating signal; and voltage tuning capacitor bank, for performing phase-locking in response to the filtered signal; and the frequency divider, coupled to the oscillating module and the phase frequency detector, for dividing the frequency of the output oscillating signal by the divider value to generate the divided signal; a scalar circuit, coupled to the PLL circuit, for receiving modulating data and generating the first control signal in response to the modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form; a sigma-delta modulator for receiving the same modulating data and generating the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit; a phase quantizer, for quantizing the phase difference information between reference signal and divided signal to generate quantized phase difference information in digital format; and a calibration circuit, coupled to the phase quantizer, for calibrating an estimated tuning gain of the oscillating module in response to the quantized phase difference information.