| 摘要 |
PROBLEM TO BE SOLVED: To restrict fluctuations of a sampling delay and restrict harmonic distortions in a parallel type A/D converter, for example. SOLUTION: With a configuration, output signals of a transfer part 24 which constitutes a latch step 6, i.e., differential signals ZP, ZN, are subjected to a negative feedback to a comparison step 4 through a feedback circuit 8 which comprises a differential amplifier circuit with transistors Q3 , Q4 . Thus, an amplitude of an input signal of the transfer part 24 is stabilized, without having to use the slew rate of an input signal VIN, for example. When the slew rate is high, the amplitude is restricted, and when it is low, the amplitude is strengthened. As a result, fluctuations of sampling delay relating to sampling clocks CLKP, CLKN are restrained.
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