Multiple mode memory module

摘要

A memory control unit is coupled during use to a system bus for receiving memory addresses therefrom. The memory control unit is further coupled during use to one or more memory units by a second bus that includes a plurality of signal lines for transmitting, during a memory access cycle, a memory address to the one or more memory units. Each of the one or more memory units includes a plurality of semiconductor memory devices having a plurality of addressable memory storage locations. The memory control unit further includes circuitry that is responsive to a signal asserted by one of the memory units. The asserted signal indicates an access speed of the selected memory unit. The memory control unit specifies a duration of a memory access so as to make the duration of the memory access cycle compatible with the indicated access speed of at least the semiconductor memory devices of the selected memory unit.