发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT TEST DEVICE AND METHOD
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit test device and its method capable of efficiently performing a test of an object of writing, reading and eliminating the data, by a unit of a block of a specific size of a flash memory and the like. SOLUTION: This device comprises a bad block determining part 15 for determining an unusable block (bad block) of a tested memory 20 on the basis of a result of comparison of contents of an output signal SG6 from the tested memory 20 and an expected value included in an expectation signal SG5, and storing a block address for specifying the block. A sequence control part 10 performs the control to stop the test to the block, when the address outputted from a pattern generating part 11 is included in the block specified by the block address stored in the bad block determining part 15. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003194891(A) 申请公布日期 2003.07.09
申请号 JP20010399677 申请日期 2001.12.28
申请人 ANDO ELECTRIC CO LTD 发明人 KAWARASAKI FUTOSHI
分类号 G01R31/28;G11C29/00;G11C29/56;(IPC1-7):G01R31/28 主分类号 G01R31/28
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