| 摘要 |
PROBLEM TO BE SOLVED: To provide the pattern generating device and method capable of easily generating a pattern such as an address complement pattern without a limit in a maximum value of a line address and a row address, and to provide a semiconductor integrated circuit test device. SOLUTION: A line address operating circuit 30a performs the operation in accordance with the line address operation command S31, and outputs an operation result S41. A line maximum value register 31a stores the maximum value of the line address. A subtracting circuit 32a outputs a subtraction result S61 obtained by subtracting the operation result S41 from the maximum value stored in the line maximum value register 31a, and selects one of the operation result S41 and the subtraction result S61 on the basis of a selecting signal S31. A constitution composed of a row address operating circuit 30b, a line maximum value register 31b, a subtracting circuit 32b and a selecting circuit 33b are also similarly operated. COPYRIGHT: (C)2003,JPO
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