| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that the latchup of a CMOS can not be prevented readily while keeping miniaturization. SOLUTION: A CMOS composed of first and second FETs 1, 2 has N-type and P-type latchup prevention regions 8, 12. The first and second FETs 1, 2 are arranged parallel in a first direction viewed planar. A P-type source region 6 and a P-type drain region 7 are arranged in opposition in a second direction at right angles to the first direction. An N-type source region 10 and an N-type drain region 11 are arranged opposite to each other in the second direction. The N-type and P-type latchup prevention regions 8, 12 are arranged between the P-type source region and drain region and the N-type source region and drain region respectively, and formed also under a gate connection conductor layer. COPYRIGHT: (C)2003,JPO
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