发明名称 SYSTEM INDEPENDENT AND SCALABLE PACKET BUFFER MANAGEMENT ARCHITECTURE FOR NETWORK PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide system independent and scalable packet buffer management architecture for network processors. SOLUTION: A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed and a packet-processing address register in each network processor identifying the packet being processed by the network processor. N-bit address to the buffer are mapped or masked from/to m-bit packet-processing address registers by software, thereby enabling the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor retrieves a new packet for processing by using the next packet address register and copies the packet into the related packet- processing address register in order to use the packet in subsequent accesses. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003229887(A) 申请公布日期 2003.08.15
申请号 JP20020377571 申请日期 2002.12.26
申请人 STMICROELECTRONICS INC 发明人 KARIM FARAYDON O;CHANDRA RAMESH;STRAMM BERND H
分类号 G06F12/02;H04L12/46;H04L12/56;(IPC1-7):H04L12/56 主分类号 G06F12/02
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