发明名称 |
LIBRARY, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND LOGIC FORMING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To provide a logic forming method for semiconductor integrated circuits which solves the malfunctioning due to noise and reduces the power consumption. SOLUTION: The method comprise the steps of: selecting a first circuit constitution of serial type AND gates, etc., from a library (201); executing a simulation of the circuit operation for the circuit constitution (202); using the first circuit constitution as it is, if the noise level of an intermediate node (precharge node) is less than a threshold (204); or selecting second constituent elements such as parallel type AND gates, if the noise level of the precharge node is not less than the threshold (205); and thereby determining a logic circuit for use (207). COPYRIGHT: (C)2004,JPO
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申请公布号 |
JP2003283330(A) |
申请公布日期 |
2003.10.03 |
申请号 |
JP20020086794 |
申请日期 |
2002.03.26 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
YANO JUNICHI;INOUE GENICHIRO;NAKAMURA KAZUYOSHI |
分类号 |
H01L21/822;H01L21/82;H01L27/04;H03K19/20;(IPC1-7):H03K19/20 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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