| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a design method for a semiconductor integrated circuit capable of easily preparing a clock tree. <P>SOLUTION: Template areas Ret1, Ret2, and Ret3 in functional blocks BL1, BL2, and BL3 presents sizes of clock trees CT1, CT2, and CT3. Though shapes thereof when a template size is set small and when set large are geometrically similar to each other, lengths of wirings between clock buffers and between flip-flop buffers are differentiated from each other. When the lengths of the wirings are differentiated, the delay time of the wiring is varied, and the shorter the length of the wiring, the shorter the delay time of the wiring is. The size of the template matching a requested clock skew value and the delay time value of the clock tree, the type of the clock buffer inserted therein, and the position of a tapping point are determined. <P>COPYRIGHT: (C)2004,JPO</p> |
