Parallel automatic synchronization system (PASS)

摘要

A parallel automatic synchronization system includes a variable delay devices for receiving and variably delaying N parallel transmitted channel data words over repetitive clock cycles in response to a synchronization latch clock and for synchronously clocking out the parallel data words by a local reference clock (FREF); sync logic devices for receiving repetitive control clocks corresponding to the transmitted channel data words, including a remote recovered clock (FFRM) and the local reference clock (FREF) and for generating the synchronization latch clock which determines the delay position of the variable delay of the delay devices; and output latch devices for clocking out the parallel data words from the variable delay devices with the local reference clock (FREF).