| 摘要 |
A piezoelectric wafer clamping system for securing semiconductor wafers during the integrated circuit manufacturing processes. The piezoelectric wafer clamping system includes a plurality of piezoelectric stack assemblies designed for providing a real time adjustable vertical clamping force to a semiconductor wafer, an annular wafer clamp member coupled to each one of the plurality of piezoelectric stack assemblies and positionable to abut a top surface of a semiconductor wafer, a wafer support assembly designed for supporting the semiconductor wafer during processing, and a control assembly to monitor and compare actual cooling gas process parameters with preset process chamber parameters and electronically regulate a vertical clamping force applied by the plurality of the piezoelectric stack assemblies.
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