发明名称 Integrated circuit chip and fabrication method
摘要 An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.
申请公布号 US9455239(B2) 申请公布日期 2016.09.27
申请号 US201514743072 申请日期 2015.06.18
申请人 STMicroelectronics (Crolles 2) SAS 发明人 Chapelon Laurent-Luc;Cuzzocrea Julien
分类号 H01L23/00;H01L21/768;H01L23/48;H01L23/528 主分类号 H01L23/00
代理机构 Gardere Wynne Sewell LLP 代理人 Gardere Wynne Sewell LLP
主权项 1. An integrated circuit chip, comprising: a substrate die; integrated circuits and a layer incorporating a front electrical interconnect network on a front face of the substrate die; at least one rear electrical connection structure comprising: an electrical connection via passing through the substrate die and linked to a connection portion of said front electrical interconnect network;a rear electrical connection pillar formed on the electrical connection via;a local rear protection layer at least partly covering the electrical connection via and the electrical connection pillar; andwherein the electrical connection via and the rear electrical connection pillar are formed of a same metal material.
地址 Crolles FR