| 摘要 |
When a field is determined by using a counter, a number of gates are needed in fabricating the counter and accordingly, the circuit scale is magnified and high cost formation is resulted. According to the invention, in a timing control circuit for separating a horizontal synchronizing signal and a vertical synchronizing signal included in a compound synchronizing signal CSYNC by a synchronizing separator circuit and forming an internal horizontal synchronizing signal and an internal vertical synchronizing signal based on a horizontal synchronizing signal Sep-HD and a vertical synchronizing signal Sep-VD after the separation, pulses P2 and P3 formed in a procedure of synchronizing separation at the synchronizing separator circuit, are utilized for determining a field in a field determining circuit and when the compound synchronizing signal CSYNC is inputted as an external synchronizing signal, whether the field is an odd number field or an even number field is determined.
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