| 摘要 |
PURPOSE: A delay locked loop(DLL) circuit is provided to control each delay unit according its operation characteristics and also to reduce the number of converted bits. CONSTITUTION: A clock buffer(310) generates a clock input signal by receiving an external clock signal. A plurality of coarse delays(321,322) receive the first control signal and the clock input signal, and generate a coarse delay clock signal by delaying the clock input signal according to the first control signal. A fine delay(330) receives the second control signal and the coarse delay clock signal, and generates a fine delay clock signal by delaying the coarse delay clock signal according to the second control signal. An output buffer(340) stores the fine delay clock signal. A delay monitor(350) compensates a time difference between an external clock and an internal clock by receiving the fine delay clock signal, and thus generates a compensated clock signal. A phase detector(360) generates a comparison signal by comparing the clock input signal with the compensated clock signal. A phase control part(370) generates a phase control signal. A variable up-down counter(380) generates the first counter signal and the second counter signal. The first decoder(391) decodes the first counter signal and then outputs it to the plurality of coarse delays. And the second decoder(392) decodes the second counter signal and then outputs it to the fine delay.
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