发明名称 Memory reference estimation method and device based on improved cache
摘要 A computer system that includes a processor, a memory and a processor cache for the main memory with a check-in-cache instruction may be provided. The processor executes computer readable instructions stored in the memory that include receiving a check-in-cache instruction from a check-in-cache storage location. The instructions also include responsive to receiving the check-in-cache instruction, determining whether data bytes specified by the check-in-cache instruction are at least partially available in the processor cache. The instructions further include storing a condition code of the determination result in a storage location.
申请公布号 US9460011(B1) 申请公布日期 2016.10.04
申请号 US201514967595 申请日期 2015.12.14
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Kraemer Marco;Otte Carsten;Raisch Christoph
分类号 G06F12/00;G06F12/08;G06F12/12 主分类号 G06F12/00
代理机构 Cantor Colburn LLP 代理人 Cantor Colburn LLP ;McNamara Margaret
主权项 1. A computer system comprising: a memory having computer readable instructions, the memory including a main memory; a processor cache for the main memory; and a processor for executing the computer readable instructions, the computer readable instructions comprising: receiving a check-in-cache instruction from a check-in-cache instruction storage location; and responsive to receiving the check-in-cache instruction, determining whether data bytes specified by the check-in-cache instruction are at least partially available in the processor cache without accessing the processor cache data or loading data to the processor cache, storing a condition code of the determination result in a storage location.
地址 Armonk NY US
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