发明名称 |
Ultra high-speed DDP-SRAM cache |
摘要 |
An ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache having a cache speed in approximately the GHz range. This is accomplished by (1) a specially designed dual-port SRAM whose size is slightly larger than that of a conventional single port SRAM, and (2) the use of a dual dual-port SRAM architecture which doubles its speed by interleaved read and write operations. A first embodiment provides a 6-T (transistor) all nMOS dual-port SRAM cell. A second embodiment provides a dual port 7T-SRAM cell which has only one port for write, and both ports for read.
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申请公布号 |
US6751151(B2) |
申请公布日期 |
2004.06.15 |
申请号 |
US20010827073 |
申请日期 |
2001.04.05 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HSU LOUIS L.;KIRIHATA TOSHIAKI K.;WANG LI-KONG;WONG ROBERT C. |
分类号 |
G06F12/08;G11C8/16;H01L27/11;(IPC1-7):G11C8/00;G11C11/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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