发明名称 |
Semiconductor memory having dynamic memory cells and a redundancy relief circuit |
摘要 |
A semiconductor memory capable of reducing refresh cycle time, which includes normal memory cells provided at predetermined intersections of plural normal word lines and plural bit lines, and redundant memory cells of redundant word lines and the plural bit lines, a redundancy relief circuit evaluates whether each of an internal address signal for a memory operation and a refresh address signal corresponds to the address of a defective word line of the plural normal word lines. An address selecting circuit switches the defective word line to a redundant word line according to the evaluation result. The redundancy relief circuit then evaluates whether a refresh address added to the refresh address signal corresponds to a defective address, and during refresh, the address selecting circuit selects a normal or redundant word line according to the evaluation result in a preceding cycle.
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申请公布号 |
US6762963(B2) |
申请公布日期 |
2004.07.13 |
申请号 |
US20020192615 |
申请日期 |
2002.07.11 |
申请人 |
RENESAS TECHNOLOGY CORPORATION;HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
INOUE YOSHIHIKO;MOTOMURA HISASHI;HORIGUCHI MASASHI |
分类号 |
G11C11/401;G11C11/403;G11C11/406;G11C29/04;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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