发明名称 Image processing circuit, has RAM management interface connected to bus system which exchanges data between RAMs, where distribution of access flow to RAM between two buses is according to use
摘要 <p>The circuit has a RAM management interface connected to a bus system which exchanges data between RAMs and to an input-output interface and a computing unit. A bus image exchanges data between the RAM and a specific module for processing pre-programmed images. Distribution of access flow to the RAM between the two buses is according to use, and minimum access flow is guaranteed to each of the two buses.</p>
申请公布号 FR2852440(A1) 申请公布日期 2004.09.17
申请号 FR20030003061 申请日期 2003.03.12
申请人 TAK'ASIC 发明人 VERNIERE JEAN PAUL;GAUTIER PHILIPPE;PAUCARD BRUNO;LE MAITRE DIDIER
分类号 G06F3/14;G06T1/60;G09G5/36;(IPC1-7):G11C7/10 主分类号 G06F3/14
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