| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To achieve a self-synchronizing block processor which can dispense with the optimization of a clock route for distributing to each block, and suppress the increase of circuit size, and can suppress the increase of design period by way of circuit tuning, in higher-level clock phase management. <P>SOLUTION: A local block control circuit 1 is provided with a completion detection unit 12 which receives two or more complete signals 22; a transfer control unit 11 which receives an end signal 13 outputted from the completion detection unit 12, a system clock 10, and a handshake control signal 6, and generates a stop signal 14 of negative logic which decides whether or not the system clock 10 is to be supplied to a processing block 2; and a logical AND gate 15 which generates an in-block clock 20 on the basis of the stop signal 14 of negative logic outputted from the transfer control unit 11 and the system clock 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
