发明名称 ERROR DETECTION APPARATUS AND METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To overcome the problem that a circuit scale is expanded by increasing computational complexity when a differential square law sum is used although a motion vector can be highly accurately detected when the differential square law sum is used rather than a differential absolute value sum between pixel data of a present frame and pixel data of a reference frame is used, in the detection. <P>SOLUTION: When detecting an error between an evaluation aggregate and a reference aggregate, the error is dissolved into bit planes and a value of each bit plane is weighted with a weight coefficient that is an arbitrary real number value to approximate the differential square law value and the differential absolute value between the evaluation aggregate and a reference value of the reference aggregate. Thus, in the error detection method and apparatus, the error is highly accurately detected while suppressing the expansion of the circuit scale in the error detection between the evaluation value and the reference value. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2004328641(A) 申请公布日期 2004.11.18
申请号 JP20030124050 申请日期 2003.04.28
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 AKIYAMA TAKASHI;SHIGESATO TATSURO
分类号 H04N19/50;G06T7/20;H04N19/51;H04N19/513;(IPC1-7):H04N7/32 主分类号 H04N19/50
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