| 摘要 |
This present invention is directed to a stage circuit for a pipelined analog-to-digital converter. The stage circuit includes an amplifier, a comparator, a first compensator and a second compensator, and three modes are developed for the stage circuit in signal processing: a sampling mode, a first amplifying mode and a second amplifying mode. In the sampling mode, the amplifier is inputted with an analog input signal; the comparator compares the analog input signal with a reference signal, and then generates a first digital output code. In the first amplifying mode, the first compensator selectively adds a first compensation value to the analog input signal according to the first digital output code, and then generates a first input signal; the amplifier amplifies the first input signal and then generates a first output signal; the comparator compares the first output signal with the reference signal and then generates a second digital output signal. In the second amplifying mode, the first compensator selectively adds a second compensation value to the analog input signal according to the first digital output code and the second digital output code, and then generates a second input signal; the amplifier amplifies the second input signal and then generates a second output signal; the second compensator selectively chooses a third compensation value according to the first digital output code and the second digital output code, and the third compensation value is amplified and added to the second output signal to generate an analog output signal which sends to the next stage circuit.
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